1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to a method and system for accurate alignment of integrated circuits in a flip-chip configuration.
2. Description of the Relevant Art
Fabrication of integrated circuits upon semiconductor wafers involves numerous processing steps. For example, the fabrication of a metal-oxide-semiconductor (xe2x80x9cMOSxe2x80x9d) integrated circuit includes the formation of trench isolation structures within a semiconductor wafer, generally a silicon wafer, to separate each MOS field-effect transistor (xe2x80x9cMOSFETxe2x80x9d) that will be made. The wafer is typically doped with either n-type or p-type impurities. A gate dielectric, typically composed of silicon dioxide, is formed on the surface of the wafer. For each MOSFET being made, a gate conductor is formed over the gate dielectric and a source and drain are formed by introducing dopant impurities into the wafer. Conductive interconnect lines are then formed to connect the MOSFETs to each other and to the terminals of the completed integrated circuit. Modern high-density integrated circuits typically include multiple interconnect levels to provide all of the necessary connections. Multiple interconnect levels are stacked on top of each other with intervening dielectric levels providing electrical insulation between interconnect levels.
During manufacture of an integrated circuit (e.g., a microprocessor), interconnect lines formed upon a wafer which are to be connected to external devices are terminated at flat metal contact regions called input/output (I/O) pads (these pads are also referred to as xe2x80x9cbonding padsxe2x80x9d herein). Following manufacture, the integrated circuit is typically secured within a protective semiconductor device package. In addition to providing mechanical, electromagnetic, and chemical protection for the circuit, a package typically provides connections between the circuit and a printed circuit board to which it is attached, and may also assist with dissipation of heat from the circuit. Some types of device packages have terminals called xe2x80x9cpinsxe2x80x9d for insertion into holes in a printed circuit board. Other types of device packages have terminals called xe2x80x9cleadsxe2x80x9d for attachment to flat metal contact regions on an exposed surface of a printed circuit board. Each bonding pad of a circuit to be packaged is connected to one or more contact pads on the IC-mounting, or xe2x80x9cmountingxe2x80x9d surface of the device package (typically the side of the package opposite the side connected to the circuit board). Traditionally the contact pads of device packages have been arranged about the periphery of the package, and bonding pads of a circuit have been arranged at the periphery of the circuit. Fine metal wires are typically used to connect the bonding pads of the circuit to the contact pads of such a device package, in a process known as wire bonding.
More recently, a different packaging geometry known as xe2x80x9cflip chipxe2x80x9d packaging is increasingly employed. A flip chip as used herein is an integrated circuit (also called a xe2x80x9cchipxe2x80x9d or xe2x80x9cdiexe2x80x9d) mounted onto a substrate in such a way that the processed surface of the circuit (the surface upon which the transistors are formed, as opposed to the back side of the circuit) is facing the substrate onto which the circuit is mounted. In other words, a flip chip is mounted onto a substrate xe2x80x9cupside downxe2x80x9d as compared to a wire-bonded circuit, which is said to be in a xe2x80x9cdie-upxe2x80x9d configuration. Similarly, circuits mounted in a flip-chip geometry are also said to be in a xe2x80x9cdie-downxe2x80x9d configuration. Several features of the flip-chip packaging configuration make it attractive for packaging of high-performance circuits. A commonly used flip chip technology is the solder-bumped flip-chip technology, also known as xe2x80x9ccontrolled-collapse chip connectionxe2x80x9d, or xe2x80x9cC4xe2x80x9d. In this process, solder bumps or balls are formed on the bonding pads of the circuit. The bumps are placed in contact with the corresponding contact pads of the substrate to which the circuit is to be mounted, and heat is applied to form solder connections to mount the circuit to the substrate. Unlike the wire-bonding process, formation of solder bumps may be done on bonding pads arranged above active areas of a circuit without damaging the underlying circuitry. Bonding pads for flip-chip packaging may therefore be arranged in a two-dimensional array across the integrated circuit, rather than being limited to the periphery of the circuit. The circuit, or die, may itself therefore be smaller than a comparable wire-bonded circuit. Similarly, the flip-chip mounting of the circuit onto a substrate allows the contact pads on the substrate to be directly aligned with the corresponding bonding pads on the circuit, rather than outside the periphery of the circuit as with wire-bonded packaging. The size of the package is therefore also reduced as compared to the package needed for a wire-bonded circuit. This reduced die and package size reduces overall integrated circuit cost. Furthermore, flip chip packaging generally provides improved electrical performance as compared to wire-bonded packaging, because the solder connections are shorter than wire bonds and typically exhibit reduced resistance, capacitance and inductance.
A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. Many modem day processes employ features, such as gate conductors and interconnects, which have less than 0.3 xcexcm critical dimension. As feature size decreases, the sizes of the resulting transistors as well as those of the interconnects between transistors also decrease. Fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area. This reduction in transistor size necessitates more bonding pads on a circuit for a given die size, and this in turn may cause smaller bonding pads to be required. Various factors may limit the quantity and size of bonding pads on the integrated circuit (and of the corresponding pads on the substrate). For example, the size of a bonding pad may be limited by how small the solder bump formed on the bonding pad can be made. Furthermore, the spacing between bonding pads may be limited by space needed for thermal expansion of the solder connections during the thermal cycling which occurs during packaging, testing and operation of the integrated circuit.
The size and/or spacing of bonding pads could also be limited by the alignment accuracy achievable when connecting the bonding pads to the corresponding contact pads on the substrate. Such alignment accuracy has not historically been considered extremely important in flip-chip packaging, because the bonding pad density has been small enough that alignment requirements have not been severe. For example, the pitch of a bonding pad array used in a current C4 process may be as large as 100 microns or greater. xe2x80x9cPitchxe2x80x9d as used herein refers to the distance between a point on an element in an array (such as an bonding pad or contact pad) and the corresponding point on an adjacent element in the array. For example, the center-to-center distance between adjacent bonding pads in an array corresponds to the pitch of the array. In addition to the relatively large bonding pad spacings used historically, flip-chip solder bump connections benefit from a self-alignment property of the solder connection. Because the solder preferentially xe2x80x9cwetsxe2x80x9d the metal bonding pads and contact pads as opposed to the surrounding insulator, the surface tension of the solder tends to move the chip into alignment over the substrate during the heating process which forms the connections between the bonding pads and the contact pads on the substrate, as long as there is some initial overlap between the solder bump on the bonding pad and the metal contact pad.
As integrated circuit features continue to get smaller, however, it is believed that current limitations on bonding pad density, such as solder bump formation technology and solder bump thermal expansion, will be overcome so that bonding pads and the corresponding substrate contact pads will continue to decrease in size and be placed closer together. This reduction in bonding pad size and spacing may make alignment accuracy much more critical. For example, the self-alignment property of the solder connection formation is of little use if no overlap between the bonding pad and the corresponding contact pad is achieved. In some cases, the bonding pad could be positioned to overlap not with the corresponding contact pad, but with an incorrect adjacent contact pad. It would therefore be desirable to develop a method and system for more accurate alignment of circuits to substrates for flip chip mounting.
The problems outlined above are in large part addressed by a method in which a circuit alignment feature on the processed surface of the integrated circuit and a substrate alignment feature on the mounting surface of a substrate are used to accurately align a set of bonding pads on the processed surface with a corresponding set of contact pads on the mounting surface. The xe2x80x9csubstratexe2x80x9d upon which the integrated circuit is mounted, as used herein, is typically a packaging substrate such as a ball grid array substrate. In some embodiments, however, a circuit may be mounted directly to a circuit board. Accordingly, the substrate is a circuit board in such an embodiment. The mounting surface of the substrate is the surface upon which the integrated circuit is mounted. The position of an alignment feature on the integrated circuit, and the position of an alignment feature on the substrate are determined. Knowledge of these alignment feature positions is used to achieve a predetermined separation, in a plane parallel to the surface of either the substrate or circuit, between the circuit alignment feature and the substrate alignment feature.
Use of such alignment features is believed to allow substantially greater alignment accuracy than techniques currently used for flip-chip mounting of integrated circuits to substrates. For example, an alignment error of less than one micron (before any additional self-alignment occurs during the solder connection formation) is believed to be achievable using the method and apparatus described herein. Such an error is believed to be much smaller than alignment errors exhibited by current methods of flip-chip circuit packaging. The alignment features may include alignment marks formed upon the circuit and/or substrate specifically for the purpose of flip-chip alignment. The alignment features may also include other features on the integrated circuit, such as the edge of a die seal around the integrated circuit, the edge of a contact pad on the substrate, or a alignment mark formed on the integrated circuit for alignment of masks during processing performed prior to packaging of the circuit. Although use of alignment features is known in the art of fabrication of integrated circuits, these features are not believed to be currently used for the process of packaging the circuits.
In an embodiment of the method described herein, the positions of the alignment features may be observed using a camera. Separate cameras may be used for determining the position of the circuit alignment feature and that of the substrate alignment feature. In some embodiments, more than one alignment feature is located on each of the circuit and the substrate. Such use of more than one feature is believed to be advantageous in obtaining an accurate rotational position of the set of bonding pads on the circuit with respect to the set of contact pads on the substrate.
An apparatus for mounting an integrated circuit is also contemplated herein. A circuit fixture is adapted to hold the integrated circuit, and a substrate fixture is adapted to hold the substrate on which the circuit is to be mounted. The apparatus also includes an alignment feature detection system to determine positions of a circuit alignment feature on the processed surface of the integrated circuit and a substrate alignment feature on the mounting surface of the substrate. An alignment controller is adapted to move the circuit fixture with respect to the substrate fixture such that a set of bonding pads on the processed surface of the integrated circuit is aligned with a corresponding set of contact pads on the mounting surface of the substrate. The alignment includes achieving a predetermined separation, in a plane parallel to that of the processed surface or mounting surface, between the circuit alignment feature and the substrate alignment feature. The error in the alignment may be less than one micron. The alignment feature detection system may include, for example, a camera or a light source and detector. In an embodiment, one camera is mounted within the circuit fixture and oriented to face the substrate, while another camera is mounted within the substrate fixture and oriented to face the circuit.
In addition to the method and apparatus described above, a circuit structure is contemplated herein. An integrated circuit having a set of bonding pads arranged upon its processed surface is mounted onto a substrate in such a way that each of the bonding pads is connected to a corresponding contact pad arranged upon the mounting surface of the substrate. The structure further includes a circuit alignment feature on the processed surface of the integrated circuit, where the circuit alignment feature has a predetermined separation, in a plane parallel to that of the processed surface or the mounting surface, from a substrate alignment feature arranged upon the mounting surface of the substrate. The bonding and contact pads are preferably connected using a solder connection, and the pitch of the contact pads on the substrate (and accordingly the bonding pads on the circuit) may be less than about 10 microns.